Austrochip 2017

25th Austrian Workshop on Microelectronics
October 12th, 2017 - Linz, Austria

Johannes Kepler University
IIC - Institute for
Integrated Circuits

Austrochip 2017 Conference Program:

08:00 - 09:00 Registration and Breakfast
09:00 - 09:15 Conference Opening
09:15 - 09:35 Keynote Address
  • Gerhard Riess (Infineon)
09:40 - 10:00 Keynote Address
  • Dr. Manfred Sust (RUAG Space)
10:00 - 10:45 Session I: Device Modelling and Verification
  • Analysis of semiconductor process variations by means of Hierarchical Median Polish
    Benjamin Willsch, Julia Hauser, Stefan Dreiner, Andreas Goehlich, Holger Kappert and Holger Vogt

  • DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework
    Fabian Horst, Atieh Farkokhnejad, Michael Graef, Fabian Hosenfeld, Gia Vinh Luong, Chang Liu, Qing-Tai Zhao, Francois Lime, Benjamin Iniguez and Alexander Kloes
10:45 - 11:05 Coffee Break, Exhibition
11:05 - 13:00 Session II: RF Integrated Circuit Design
  • A Compact, Low Power and High Sensitivity E-Band Frequency Divider SiGe HBT MMIC
    Aleksey Dyskin, Parisa Harati and Ingmar Kallfass

  • CMOS Open-Loop Local Quadrature Phase Generator for 5G Applications
    Michael Kalcher and Daniel Gruber

  • Receiver Chip in 0.6µm BiCMOS with AGC and LVDS Output Driver
    Bernhard Goll, Robert Swoboda and Horst Zimmermann

  • A Circuit Technique for Blocker-Induced Modulated Spur Cancellation in 4G LTE Carrier Aggregation Transceivers
    Silvester Sadjina, Dufrene Krzysztof, Ram Kanumalli, Mario Huemer and Harald Pretl

  • A Review of Ultra-Low-Power and Low-Cost Transceiver Design
    Tim Schumacher, Markus Stadelmayer, Thomas Faseth and Harald Pretl
13:00 - 14:30 Lunch, Exhibition
14:30 - 14:50 Keynote Address
  • Dr. Christoph Guger (g.tec)
14:50 - 15:35 Session III: Digital Circuit Design and System Verification
  • A FPGA-based Demonstrator for Safety-Critical Applications
    Christian Fibich, Peter Roessler, Stefan Tauner, Martin Matschnig and Herbert Taucher

  • Using Python tools to assist mixed-signal ASIC design and verification methodologies
    Evangelos Logaras and Andreas Weitzer
15:35 - 16:10 Coffee Break, Exhibition
16:10 - 17:40 Session IV: Analog and Mixed-Signal Circuit Design
  • Implementation of a Charge-Controlled Method in a Monolithic Integrated CMOS-Chip for Excitation of Retinal Neuron Cells
    Andreas Erbslöh, Reinhard Viga, Peter Walter, Rainer Kokozinski and Anton Grabmaier

  • Measurement and Comparison of several Pass Transistor Logic Styles in a 350nm technology
    Andreas Rauchenecker and Timm Ostermann

  • Implementation of an integrated differential Readout Circuit for transistor-based Physically Unclonable Functions
    Benjamin Willsch, Kai-Uwe Müller, Qi Zhang, Stefan Dreiner, Alexander Stanitzki, Holger Kappert, Rainer Kokozinski and Holger Vogt

  • Survey on Integrated High Power Low Emission Output Stages for Drivers of Low-Frequency Resonant Loads
    Herbert Hackl
17:40 - 17:50 Outlook Austrochip 2018